1. Field
Example embodiments relate to semiconductor memory devices and methods of manufacturing the semiconductor memory devices. Other example embodiments relate to charge trapping type non-volatile memory devices having charge trapping layer patterns for storing charges therein, and methods of manufacturing the charge trapping type non-volatile memory devices.
2. Description of the Related Art
Generally, non-volatile semiconductor memory devices may be divided into floating gate type non-volatile memory devices and charge trapping type non-volatile memory devices in accordance with structures of unit memory cells thereof. The charge trapping type memory device may have a silicon oxide nitride oxide semiconductor (SONOS) structure, and thus the charge trapping type memory device may be referred to as an SONOS type non-volatile memory device. In the floating gate type memory device, the unit memory cell may include a tunnel oxide layer formed on a semiconductor substrate, a floating gate, a dielectric layer and a control gate. Data may be stored into the floating gate as free charges are injected into the floating gate.
In the charge trapping type non-volatile memory device, the unit memory cell may include a tunnel oxide layer formed on the semiconductor substrate, a charge trapping layer, a dielectric layer and an electrode. Data may be stored into the charge trapping non-volatile memory device as charges are injected into charge trapping sites of the charge trapping layer. The charges may be trapped in deeper level trapping sites of the charge trapping layer such that the tunnel oxide layer may have a relatively thin thickness. When the tunnel oxide layer is relatively thin, the charge trapping type non-volatile memory device may be operated with a decreased voltage and also a peripheral circuit of the charge trapping type non-volatile memory device may have a simpler structure. The charge trapping type non-volatile memory device may be highly integrated in comparison with the floating gate type non-volatile memory device.
As for the conventional charge trapping type non-volatile memory device, a charge trapping structure of a cell transistor in a cell area may be different from a gate structure of a metal oxide semiconductor (MOS) transistor in a peripheral circuit area, so that manufacturing processes for forming the charge trapping structure and the gate structures may be somewhat complicated. A recent charge trapping type non-volatile memory device may include a metal oxide layer having a high-k dielectric constant as a dielectric layer instead of a conventionally used silicon oxide layer. An electrode of doped polysilicon may not be properly formed on the dielectric layer of metal oxide, because the electrode of the doped polysilicon on the metal oxide layer may not have a sufficient work function due to Fermi-level pinning phenomenon. The electrode on the metal oxide layer may be formed using a conductive material having an increased work function above about 4.5 eV. A gate electrode of the MOS transistor in the peripheral circuit area may be formed using a conductive material that may have a decreased work function of about 4.0 eV to about 4.3 eV
To form the electrode in the cell area and the gate electrode in the peripheral circuit area, different conductive materials may be deposited on the cell and the peripheral circuit areas through separated deposition processes, and also the deposited different conductive materials may be respectively etched by separated etching processes. Manufacturing processes for forming the charge trapping structure and the gate structure may be complicated, thereby causing failures in the manufacturing processes. Because additional electrodes are formed on the electrode and the gate electrode, respectively, barrier metal layers may be required between the electrode and one additional electrode and between the gate electrode and another additional electrode. The barrier metal layers may not be easily formed between the electrode and one additional electrode and between the gate electrode and the other additional electrode because the barrier metal layers may be required to have improved thermal stability and a proper diffusion barrier.